1. Field of the Invention
The invention relates to an interconnect arrangement and a method for fabricating an interconnect arrangement.
Integrated circuit arrangements are produced with an ever higher packing density. The consequence of this is that there is an ever smaller distance between interconnects in metallization planes. This means that there is a rise in capacitances which are formed between the interconnects and lead to high signal propagation times, a high power loss and crosstalk. To date, SiO2 has principally been used as dielectric for insulation between the interconnects; its relative permittivity ∈r=3.9.
2. Description of the Related Prior Art
A number of methods for lowering the relative permittivity ∈r and thus for lowering the capacitance between interconnects within an interconnect plane are known, for example from [1], [2], or [3].
In accordance with the cited prior art, cavities are produced between the interconnects within an interconnect plane. The insulating dielectric which determines the capacitance between the interconnects thus has a relative permittivity ∈r which is almost equal to one. In this case, the interconnects themselves are enclosed by solid SiO2 layers at the top and bottom for the purpose of insulation.